High-Level Synthesis Tools for Xilinx FPGAs

In 2009, Berkeley Design Technology Inc. (BDTI), an independent benchmarking and analysis firm, launched the BDTI High-Level Synthesis Tool Certification ProgramTM to evaluate high-level synthesis tools for FPGAs. Such tools take as their input a high-level representation of an application (written in C or MATLAB, for example) and generate a register-transfer-level (RTL) implementation for an FPGA. Thus far, two high-level synthesis tools, AutoESL’s AutoPilot and Synfora’s PICO, have been certified under the program. BDTI’s evaluation program uses two example applications, a video motion analysis application and a wireless receiver, to evaluate high-level synthesis tools (HLSTs) on a number of quantitative and qualitative metrics. As shown in Figure 1 and Figure 2, we found that the Xilinx Spartan-3A DSP 3400 FPGA used with either of the two HLSTs provided roughly 40X better performance than a mainstream DSP processor, and that the high-level synthesis tools were able to achieve FPGA resource utilization levels comparable to hand-written RTL code. Furthermore, as we will discuss in this white paper, implementing our video application using the HLSTs along with Xilinx FPGA tools required a similar level of effort as that required for the DSP processor. This finding will no doubt be surprising to many, as FPGAs have historically required much more development time than DSPs. Based on our analysis, we believe that HLSTs can significantly increase the productivity of current FPGA users. For those using DSP processors in highly demanding applications, we believe that